Pulse-width modulator (PWM) circuits can be used in a variety of applications such as switching power converters. In a switching converter, the PWM circuit is typically arranged to provide a digital logic signal that has a pulse width that is a function of an analog input voltage. Example PWM circuits are illustrated in FIG. 1A and FIG. 1B.
The circuit illustrated in FIG. 1A includes a current source (I), a capacitor (C), a switching transistor (M), an inverter, a comparator (CP), an oscillator (OSC), and an SR-type flip-flop. The oscillator is arranged to set the SR-type flip-flop at regular intervals, initiating the start of the output pulse (VOUT). The inverter is arranged to provide an inverse of the output voltage (VOUT) to switching transistor M such that switching transistor M is deactivated when the output pulse is initiated. Current source I works with capacitor C to generate a voltage ramp (VC=I*t/C) to one input of comparator CP while transistor M is deactivated. Comparator CP is arranged to reset the SR-type flip-flop whenever the analog input voltage (VIN) and the voltage ramp are equal, whereby the output pulse is terminated. Transistor M discharges capacitor C after the SR-flip-flop is reset. The pulse width (PW1A) for the circuit described above with respect to FIG. 1A is given by: PW1A=VIN*C/I.
The circuit illustrated in FIG. 1B includes a bandgap voltage reference, a trans-conductance (gm) cell, a capacitor (C), a switching transistor (M), an inverter, a comparator (CP), an oscillator (OSC), and an SR-type flip-flop. The oscillator is arranged to set the SR-type flip-flop at regular intervals, initiating the start of the output pulse (VOUT). The inverter is arranged to provide an inverse of the output voltage (VOUT) to switching transistor M such that switching transistor M is deactivated when the output pulse is initiated. Current is provided to charge capacitor C from the gm cell to generate a voltage ramp (VC=(VREF1−VIN)*gm*t/C) to one input of comparator CP while transistor M is deactivated. Comparator CP is arranged to reset the SR-type flip-flop whenever a reference voltage (VREF2) and the voltage ramp (VC) are equal, whereby the output pulse is terminated. Transistor M discharges capacitor C after the SR-flip-flop is reset. The pulse width (PW1B) for the circuit described above with respect to FIG. 1B is given by: PW1B=VREF2*C/(gm*[VREF1−VIN]).